Data processing system



March 14, 1967 J. A. WEISBECKER DATA PROCESSING SYSTEM Original FiledJuly 3l, 1962 l5 Sheets-Sheet l 2 f A Aap/e555 gz/57 JOSEPH A.WEISBECKERATTORNEY March 14, 196'/ J. A. WElsBl-:CKER

DATA PROCESSING SYSTEM l5 Sheets-Sheet l Original Filed July 3l, 1962March 14, 1967 1. A. WEISBECKER DATA PROCESSING SYSTEM l5 Sheets-$heet'J Original Filed July 3l, 1962 INVENTOR. JOSEPH A. WEISBECKER LAI/@MATTORNEY March 14, 1967 J. A. WEISBECKER DATA PROCESSING SYSTEM l5Sheets-Sheet 4 original Filed July 31, 1962 JOSEPH A. WEISBECKER BY wwwATTORNEY March 14, 1967 .1. A. WEISBECKER 3,309,679

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S f? S R 5 .s R /PXA RYA RZA HFEO /70 0 f o o o l l Rm (/1 Rm n) 92,4(f) RFM/j INVENTOR. JOSEPH A. WISBECKE R ATTORNEY March 14, 1967 J. A.WEISBECKER 3,309,679

DATA PROCESSING SYSTEM Original Filed July 3l, 1962 l5 Sheets-Sheet 'f@tu fm2 TTT Tp COUNTERV FIG 5 l l l l l l TF1 TPz TPS TF4 TPS TPe CT'ETRy 'f/ 7/ y y W VAE TPB | x I i l i l s TPS L TPe W w FIG. 6

TiME PULSE GENERATOR AND TlMING INVENTOR, JOSEPH A. WEISBECKER ATTORNEY15 Sheets-Sheet Original Filed July 3l, 1962 uomevom om vom Q .O hu8 z.om ...SUS qcm .S um 53a S @e uw f @Eu ud B m35 dm H18@ :E E N535;5.37.83 @u E 53E xd uxTHwQ uz. QH 53.3 UB z meG Elu@ INVENTOR. JOSEPH A.WEISBECKER BY gti ATTQ R N EY DATA PROCESSING SYSTEM l5 Sheets-Sheet nOriginal Filed July 3l, 1962 MEMORY LOCATION CONTENTS N NH OR wN l i.. ET nu U F O N L E N xl B XAN ET A EERH.` E C =VT NRTN www UE TmRO TFS N EI E RT RETC PEI A PU PWCU RND R RO RTER E HD G ER EUST A 0 T0 TOFS .NlwFR mE WROm IRO P |LflfJ kf Il lj d OOO D|77T7O0777TO DIOOOOTTOOOO?! 0060277000076700 D 03l4 67056000 0 00 0300000000000 D30|0000000000 0.0477!00077700 4023300033400 000 0535000034500 05200045100000 000D6|23400||240 060000I2000000 0|2 0l2345670|2 0|2345670l23 00000000000||| 00000000|||| OOO a ||||||||...\|.l|.l .222222222222 00000000000000 000000000000 000 00000000000 000000000000 MEMORY UNITCONTENTS [NVEVVORy JOS EPH A. WEISBECKER ATTORNEY March 14, 1967 J. A.WEISBECKER DATA PROCESSING SYSTEM l5 Sheets-Sheet l0 Original Filed July5l, 1962 m5 VEO;

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DATA PROCESSING SYSTEM l5 Sheets-Sheet 1l TPS TPS

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STORAGE ADDRESS I AT@ W DATA OUTPUT I AT D L I STORAGE A DDR ESS I I IMRO) minn- DATA INPUT AT FIG. II

JOSEPH A. WEISBECKER ATTO RNEY March 14, 1967 J. A. WEISBECKER 3,309,679

DATA PROCESSING SYSTEM Original Filed July 3l, 1962 l5 Sheets-Sheet l2TPI I TPz I I TF3 I TF4 l I TPS WL w I TPe L M M I I EOI 'FW @www I ReSELECT| W I (Acc)|NTo ADDER AT I M R P l w E I RIP L m GPR Ew OPE-Reli?ADG) I W I SUM To BE PLACED N Acc AT a w ARITHMETIC UNIT CYCLEIM/IENTORA JOSEPH A.WEISBECKER ATTORNEY March 14, 1967 J. A, WEISBECKER3,309,679

DATA PROCESSING SYSTEM Original Filed July 31, 1962 l5 Sheets-Sheet 13NORMAL mPurs NORMAL.

:NP Ts 1 TF5 TPS CMA TF4 TPS I cMA CMA W f/ i /i/ s R s R E04 s R F l olG|=|Eoo (b) 'N500 (a) GFEO (i) NoRMAL mPuTs 5 R cFEoU) 5 R RFEC RNEo lO I O y; TPS 50m (d) Rusch) (C) TP DATA aus (s BITS) 5 R if PEX o uoRMALINPUTS 'Q sFEou W6 Z s R 5 R /ZZ Tp@ EUR I EX E00 ExEo (v) j V FIG. I5

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lNx/E/vToR. FIG. I3 JOSEPH A. wElsBEcKER ATT ORNEY l5 Sheets-Sheet 14Nn. d d MQ ou www Qu w J March 14, 1967 Original 'Filed July 5l,

March 14, 1967 J. A. WEISBECKER 3,309,679

DATA PROCESSING SYSTEM Original Filed July 3l, 1962 l5 Sheets-Sheet 15ADDRESS Bus a Icc b ECC msTRucTxoN AND ELEMEmmzY 252 250\\ DATA MEMORYOPERATION/f/ MEMORY EAD REGENERAT [AD RE EN. TE READ CYCLE liz- }R 4 Glu t t* t2 tl t2 ta DATA BUS |02 WWE CYCLE CLEAR WRITE to t z F G. I 6

DATA Bus |01 MED EO LEO F--w-SWITCH TO STATICIZlNG CIRCUTS AND EDCONTROL CIRCUITS FIG. I7

INVENTOR. JQSEPH A. WEISBECKER ATTORNEY United States Patent Olice3,309,679 Patented Mar. 14, 1967 3,309,679 DATA PROCESSING SYSTEM JosephA. Weisbecker, Cherry Hill, NJ., assignor to Radio Corporation ofAmerica, a corporation of Delaware Continuation of application Ser. No.213,781, July 31, 1962. This application June 23, 1966, Ser. No. 560,01122 Claims. (Cl. S40-172.5)

This application represents a continuation of a copending application,Ser. No. 213.781, tiled on July 31, 1962.

This invention relates to data processing systems, and particularly todata processing system of the stored program type.

Stored programmed systems are arranged to perform various functionsusing a set of instruction words. By combining these instruction wordsin various sequences (programs) the system can be directed to carry outcomplex functions. Each program consists of a particular sequence ofinstruction words. Each instruction word usually defines a specicoperation to be performed and has one or more data addresses.

An instruction is carried out in one or more steps with the number ofsteps varying with the complexity of the operation. For example, an addinstruction requires few steps while a divide instruction may requiremany steps. The execution of the instructions is a function of thecontrol unit of the machine which comprises storage elements such asflip-flops, and gating elements through which control signals arerouted.

After a system is initially designed, it often becomes apparent thatincreased efficiency or reduced cost could be achieved by differentinstruction routings. ln most instances, these changes cannot be readilyincorporated in the designed machine `because of the amount of rewiringinvolved in changing the control unit.

The major design etfort in constructing a data processing system isconcerned with the control unit since, in the average case, severalthousand separate gates and numerous ilip-tlops are used. The gates andflip-hops are wired into logical networks so that any specifiedinstruction is properly sequenced.

The control signals generated by the control unit then serve to routedata to and from various functional units such as the arithmetic unit,buffers, peripheral devices, and so on. lt is obvious that once acontrol unit is thus wired, it is difficult to change the instructioncomplement and the manner of their execution because of the extensiverewiring of the logical gates and flip-Hops.

Further, once the control unit is wired for operation with particulartype functional units, then it is uneconomic to change from one typefunctional unit to another. For example in a particular application, itmay be desirable to replace the present arithmetic unit with anotherwhich operates at a higher speed. Hence, although it is desirable froman applications view, to have a flexible system arrangement whichpermits newer or different functional units to be used, this has notbeen possible as a practical matter in prior systems because of the timeand cost involved in changing the control unit. Moreover, in priorsystems, the use of new or different functional units systems requiresextensive reprogramming which is eX- pensive and time-consuming.

From the above, it is apparent that it is desirable to reduce as much aspossible the amount of preset wiring of the control unit. However, thisreduction in wiring, at the same time, should not accomplish acorresponding reduction in the applications for which the machine issuitable, as is the case with so-called special purpose processors.Moreover, a reduction in the amount of wiring in the control unit isdesirable because of the corresponding reduction in the testing andmaintenance required during the building and operation of the system.

It is an object of the present invention to provide a general purposedata processing apparatus wherein the control unit is appreciablysimplified with respect to prior art apparatuses of similar type.

It is another object of the present invention to provide improved dataprocessing apparatus in which the control unit requires a reduced amountof wiring and without reducing the applications for which the apparatusis suitable.

Another object of the invention is to provide improved data processingsystems, capable of being readily adapted to new applications withoutrequiring extensive rewiring.

Another object of the invention is to provide improved data processingsystems in which the various functional units can be interchanged withother functional units without requiring extensive rewiring andreprogramming of the system.

Another object of. the invention is to provide an improved dataprocessing system in which the programmer can directly control basicoperations in the system thereby permitting a variable instructionformat to be used. That is, new instructions can be generated by theprogrammer as needed.

A study of the control unit response to various instructions indicatesthat many of the machine steps generated in selecting and executing theinstructions are themselves of general purpose nature. For example, mostinstructions involve a transfer of data from one designated unit toanother. However, because the transmitting and receiving units aredifferent during different instructions, each transfer in prior systemsoften requires its own set of logical gates even though the functionsare similar. A system, according to the present invention, implementsthese basic machine steps using machine words stored in a memory unit.Each of. these machine words contains control bits necessary to set updesired conditions and to allow for execution. Each machine word isidentified by one or more bits to distinguish a machine word from aninstruction word. These machine words (termed elemen tary operations)are stored in the memory unit in a particular sequence determined by theprogrammer. The memory unit may be a magnetic core memory of therandom-access type. The "l" and "0 information bits stored in the memorycores assigned to a machine word then replace wired logical elementswhich would otherwise be required in the control unit. It is well knownthat the cost of a memory element per bit is appreciably less than thatof a logical element such as a gate or flip-Hop. Further, theinformation content of a machine word can be changed by simply erasingthe word in the memory (if the memory is of the erasable type) andinserting a new word in its place in the memory-no rewiring is involved.The effect of the new machine Word is equivalent to rewiring a controlor data path in prior art systems. lf a fixed type memory is used tostore the machine words, then any rewiring involved is greatly reducedover what was done in prior systems to change the control paths for likeresults.

An instruction in a system embodying the present invention is, then,performed according to a set of machine steps which correspond to a setof elementary operations stored in the memory.

The instruction is tirst staticized with its necessary addresses as inprior systems. Its operation code is then sensed and control istransferred to the elementary operation units which select from thememory a format of elementary operations necessary to carry out theinstruction. The control is then transferred back to the instructionstaticizing unit and the next instruction is staticized, and so on.

Each elementary operation word is read from the memory, and the controlbits decoded to provide a corresponding output level. This output levelthen activates a particular fiow path, for data, transfer or memoryaddressing, or performs a specified test for terminal conditions, and soon.

Since each instruction is now defined by a stored interpretive routineof elementary operations, the particular manner in which it is performedcan be readily changed by using a different interpretive routine of theelementary operations. Further, since the elementary operationsthemselves are of general purpose nature, a relatively small number ofthese are required to define a relatively large number of instructions.

Also, a standard system can be designed with a given complement offunctional units. This standard system can then be easily modified touse other functional units by using a different set of the interpretiveelementary operations for executing any instructions involving the newunits. However, the instruction program remains the same as that usedbefore the different set of elementary operations and no systemreprogramming is necessary. For example, a standard system using abinary adder unit can be modified to use a decimal adder unit withoutrequiring that the control unit be rewired.

Further, because the elementary operations are represented by codedmachine words in the memory, they can be handled in a manner directlyanalogous to the way instruction words are handled by present-daymachines. The coded digits representing the machine steps may bearranged to have option bits to automatically control the sequencing ofthe elementary operations themselves. Thus, with respect to theelementary operations, direct or indirect addressing, conditionalbranching among the elementary operations, data dependent loops ofelementary operations, and, so on, may be used.

Each machine step may involve a memory access in order to retrieve theelementary operation from the memory. In certain applications it isdesirable that one or more of the instructions be executed at a highspeed. In such case, it is desirable to provide logic gates arranged todirectly execute the instruction. Accordingly, the operation retrievalcircuitry of the invention may be arranged, if desired, to permit arelatively simple connection of control modules defining the particularoperations desired to be directly executed. This arrangement affords afurther degree of fiexibility and eXpandability of the basic machinedesign.

Moreover, the elementary operations can be incorporated into theinstruction program itself, if so desired, permitting the programmer astill greater flexibility in arranging the various programs for moreefficient use of the functional units.

In the accompanying drawings:

FIGURE 1 is a generalized block diagram of an arrangement of a prior artdata processing system;

FIGURE 2 is a generalized block diagram of a data processing systemaccording to the present invention;

FIGURE 3 (comprising FIGURES 3A, 3B, 3C and 3D) is a more detailedschematic diagram of a data processing system according to theinvention. The chart for assembling FIGURE 3 is indicated in FIGURE 3A.

FIGURE 4 is a schematic diagram of operation retrieval circuits used forgenerating operation levels for the system of FIGURE 3;

FIGURE 5 is a schematic diagram of a timing pulse generator forgenerating the timing pulses used in the system of the invention;

FIGURE 6 is a diagram showing the relation of the timing pulses;

FIGURE 7 is a program flow diagram of an exemplary program used inexplaining the system operation;

FIGURE 8 is a table illustrating the memory locations of instructionsand elementary operations used in executing the exemplary program;

FIGURE 9 is another table illustrating the changes in data stored atvarious memory locations during the execution of the program;

FIGURE l() is a fiow diagram illustrating the operation of the retrievalcircuits of FIGURE 9;

FIGURE ll is a timing diagram illustrating the operation of the memoryunits of FIGURE 3;

FIGURE l2 is a timing diagram illustrating the operation ofthearithmetic unit of FIGURE 3;

FIGURE I3 is a block `diagram of a modified system using fixed controlmodules for implementing certain instruetions;

FIGURE 14 is a schematic diagram of one form of instruction controlmodule useful in the system of FIG- URE 13',

FIGURE l5 is a block diagram of the modifications in the operationretrieval circuits, i.e., control circuits, when instruction controlmodules are used.

FIGURE 16 is a diagram of a system according to the invention using twoseparate memories; and

FIGURE 17 is a diagram of a system according to the invention having apair of elementary operation registers.

GENERAL For convenience of description, the invention is exemplied asembodied in a simplified processing system of the synchronous type.Further, the operation of the system is limited to a description ofseveral typical instructions, which are common to most data processingoperations. It is understood, however, that the invention is applicableto more complicated type systems including asynchronous types, and,that, in practice, many more elementary operations would be used inexecuting other instruction sequences. These additional elementaryoperations would be arranged in a manner similar to, and function in amanner similar to, those described in connection with the exemplarysystem.

Also for convenience of description, the system is assumed to benominally of the three-address type, and to have a word length ofeighteen binary digits.

DEFINITIONS The elementary operations and instruction words are definedas follows:

An EO (elementary operation) is represented by one, I8 bit word with thefollowing format in octal digits, each representing three binary digits:

D6 D5 D4 D3 D2 DI DI: Class Digit Dl must be 7(111) D12-D5: ControlDigits, respectively These digits can be used for a variety of purposes'described later for each EO type. D6: Operation Code D6 specifies thetype of operation to be executed. An instruction is represented as four,18 bit words as follows: Operation Word- D6 D5 D4 D3 D2 DI Dl: ClassDigit DI must be 0 (000) D2-D4: Control Digits, respectively D5-D6:Operation Code These digits specify the system operation (orinterpretive EO routine) to be performed. Address Words Three addresswords are associated with each operation word. These addresses areplaced in the X, Y and Z counters, respectively.

SYSTEM ELEMENTS Each of the elements used in the system is known per sein the art. Three types of logical gating gates are used, namely ancl,or and inhibit Each type of these gates may be implemented in knownfashion using diodes and transistors. See for example Chapter 16 or vol.II of Handbook of Automation, Computation and Control" by Grabbe, Ramoand Woolridge, published by John Wiley and Sons, 1959, or Chapter ofDigital Computer and Control Engineering by Robert S. Ledley, publishedby McGraw-Hill Book Company, Inc., 1960.

In the drawings, an and gate is indicated by a box with sides taperingto a point. The inputs are indicated as applied to the sides of the boxand the output is taken at the point. The and gate output is normally atone level and changes to the other level when and only when all inputsare present at the same time. For convenience, the one level may be arelatively high, positive level, representing a binary l digit. When anyone of the inputs is absent represented by a relatively low level, the"and gate output is correspondingly low, representing a binary 0 output.

An or gate is indi-cated in the drawing by a straight line having two ormore arrows on one side representing inputs and a single output line onthe opposite side. The or gate output is normally at one level, say atzero, when all the inputs represent binary zero, and changes to the one"level when any one or more of the inputs represent a binary one Aninverter circuit, represented in the drawings by a circle containing acapital I, serves to change a received high or low level representing abinary l or a binary 0 to a corresponding low or high level outputrepresenting a binary "0" or a binary 1, respectively.

The flip-dop units also are described in the above-mentioned textbooks.In the drawing a flip-Hop is represented by a rectangular block havingtwo inputs and two outputs. Each flip-Hop has set (S) and reset (R)inputs and corresponding l and 0 outputs. When the flipflop is set its"l," output is high relative to the 0 output, and when it is reset, itsU output is high relative to its "1 output.

Various decoder units are employed and each may be a one-out-of manytype matrix decoder of known, suitable design. A suitable decoder may bea diode decoder having n input pairs and 2 outputs. See, for example,Chapter 17 of the above-mentioned Ledley text.

Storage registers are also employed. Each storage register has a groupof 18 Hip-flops with separate 1iip-ops being used for each separate oneof n binary digits. These registers are also of known design.

Binary counting circuits of conventional design are also used. See, forexample, Chapter 18 of the Grabbe et al.

text. Each counter has a group of fiip-ops interconr nected to performthe binary counting function. The counter flip-tlops have set, reset andcorresponding l and 0" outputs and also have a trigger input. A signalapplied to the trigger input causes a ip-op to change from its presentstate to the opposite state. The trigger input of the counter is used toincrement the value stored in the counter one unit.

A binary adder unit also is used which functions to add two binarynumbers and to produce their sum. Suitable adder units also aredescribed in Chapter 18 of the Grabbe et al. textbook.

A comparator unit which provides a relatively high output signal whentwo equal binary input numbers are applied to its inputs is also used. Asuitable equality comparator is known. See, for example, Chapter 5, ofthe Ledley text.

A randomaccess memory is employed to store instructions, data andelementary operations. Suitable randomaccess magnetic memories areknown. See, for example, Chapter 19 of the Grabbe et al. text.

6 ABBREVIATIONS The following abbreviations are used in describing thearrangement and operation of the system of FIGURE 3.

ACC-ACCumulator AEC-Address with Elementary Counter AIC-Address withInstruction Counter AXC-Address with X Counter AYC-Address with YCounter AZC-Address with Z Counter EC-Elementary Counter EO-ElementaryOperation EOC-Elementary Operation Class EOR-Elementary OperationRegister EXEO-EXecute Elementary Operation lC-Instruction CounterINC-INstructiOn Class IR-Instruction Register OPR-OPerand RegisterREP-REset Pulse RFEO-Read First Elementary Operation RIP-Read In PulseRNEO-Read Next Elementary Operation RNIN-Read Next INstruction ROP-ReadOut Pulse RXA-Retrieve X Address RYA-Retrieve Y Address RZA-Retrieve ZAddress MW-Memory unit Write MR-Memory unit Read ST-STart TEC-TriggerElementary Counter TlC-Trigger Instruction Counter TPTime Pulse'PXC-Trigger X Counter TYC-Trigger Y Counter TZCLTrigger Z Counter XC-XCounter YC--Y Counter ZC-Z Counter GFEO-Generate First ElementaryOperation GlNI-Generate First Instruction Gti-Gate Zeroth word ofInstruction Gl-Gate First word of Instruction Cil-*Gate Second word ofInstruction (I3-Gate Third word of Instruction CMA Control Module ActiveMEO-Most Significant Elementary Operation Word LEO- Least SignicantEementary Operation Word DESCRIPTION OF FIGURE 1 SYSTEM FIGURE 1 is ageneralized block diagram of an arrangement of a stored programprocessing system according to the prior art. The system has a memoryunit 1 for storing instructions and data. Memory address signals areapplied to the memory unit via an address bus 2. The memory addressesmay be sent from inputoutput (I/O) elements 4, processing elements 5, oran instruction control (1C) counter 6. A data bus 10 is coupled betweenthe memory unit l, the input-output elements 4, the processing elements5, and an instruction register (IR) 12.

The operation of the units is controlled by instruction control circuits13 which apply signals to a control bus 14 connected between the memoryunit 1, the inputoutput elements 4, and the processing elements 5. A setof staticizing control circuits 16 are used to sequence instructions inthe instruction control counter 6, the instruction register l2, and theinstruction control circuits 13. As discussed above, the instructioncontrol circuits comprise a set of interconnected gating, nip-Hop andswitching circuits which are wired to sequence in a predetermined mannerthe instructions called for by the program.

7 DESCRIPTION OF FIGURE 2 SYSTEM FIGURE 2 is a schematic diagram of asystem according to the present invention. Similar reference numeralsare used to designate similar units.

A circuit 20 such as an elementary control counter (EC) 20 is used forsequencing elementary operations from the memory unit. Elementaryoperations are applied from data bus to an elementary operation register(EOR) 22. Elementary operation (EO) control circuits 24 respond to eachelementary operation to control the machine steps used in executing aninstruction. The wired instruction control circuits 13 of FIGURE 1 arenot required because `the sequence of sub-operation of an instructionare determined by the stored format of elementary operation words in thememory unit 1. The control circuits 24, therefore, are much lesscomplicated than in the case of the instruction control circuits 13 ofFIGURE 1.

Further, the system of FIGURE 2 provides increased flexibility over thatof FIGURE l because the coded elementary operation words in memory 1 arerelatively easily changed by clearing the previously stored set ofelementary operations, and writing a new set into the memory`DESCRIPTION OF FIGURE 3 (GENERAL) A more detailed diagram of the systemof FIGURE 2 is shown in FIGURE 3 (FIGURES 3A, 3B, 3C and 3D). In thearrangement of FIGURE 3 the various functional units are enclosed indotted blocks and identified by the same reference numeral as in FIGURE2. However, it is understood that in some cases the placement of certainelements in one or the other of the functional blocks is a matter ofconvenience since its operation may involve one or more of thefunctions. Also for convenience of drawing and description, thearrangement is simplified in that the timing and operating pulses areidealized as perfectly rectangular pulses, and delay elements which, inpractice, may be incorporated at various points in the system tocompensate for pulse propagation times and varying operation times ofthe elements are not shown. This type of compensating delay element iswell known in the art.

The memory unit 1 (FIGURE 3A) may be a randomaccess, magnetic corememory which receives or transmits data from and to the data bus 10. Thememory location for the data is designated by a group of memory addresssignals applied to the address bus 2.

During a write cycle, the memory is controlled by a memory write (MW)ip-op 26. During a read operation the memory is controlled by a memoryread (MR) ip-op 28.

Information is transferred from the memory to the data, bus 10 via a setof eighteen memory input gates 30, and from the data bus to the memoryby set of eighteen memory output gates 32.

Each counter and register unit is provided with a set of input andoutput gates for controlling entry and exit of information to and fromthe unit. The instruction counter (IC) 6 is a fifteen stage, binarycounter which has a trigger input T for incrementing it by one unit eachtime a TIC pulse is applied to the trigger input. A fifteen bit addresscode is sufficient to uniquely identify 32,000 words stored in memoryunit 1. The IC counter 6 delivers an address to address bus 2 via afirst set of fteen output gates 33, and to the data bus 10 via a secondset of fifteen output gates 34. The IC (instruction counter) 6 receivesinformation from the data bus 10 by way of a set of fifteen input gates3S, and is reset via a reset gate 36 whose output is connected to acommon reset input for the counter.

The EC (elementary counter) is a twelve stage counter incremented by aTEC pulse applied to its trigger input (T). This counter transmits datato the address bus 2 via a first set of twelve output gates 38, andtransmits information to the data bus l0 via a second set of fifteenoutput gates 39. The EC 2l) receives information from the data bus 10 byway of a set of lifteen input gates 40, and is reset by way of a resetgate 41 whose output is connected to a Common reset input.

The IC 6 and EC 20 are enabled to received information from data bus 10by way of R1 and R2 decoders 42 and 44, respectively, which arecontrolled by signals appearing on the control bus 14.

The IR (instruction register) l2 (FIGURE 3C) transmits address signalsto the address bus 2 by way of a set of six output gates 46. A classdigit Dl (bits 0-2 stored in the stages 2.022 of IR 12) is sensed bycode recognition circuits 48 and 49. The recognition circuit 48 providesan output level EOC when an elementary operation word is stored in theIR, and recognition circuit 49 provides an output INC level when aninstruction word is stored in IR 12. The instruction register 12receives data from data bus 1|] via a set of eighteen input gates 50,and is reset by a reset gate 51 whose output is connected to a commonreset input of the register.

'The EOR (elementary operation register) 22 is an eighteen stageregister which receives a word from bus l() via a set of eighteen inputgates 52. The EOR 22 transmits data to the data bus 10 via a set oftwelve output gates 53. 'The register 22 is reset by a reset gate 54whose output is connected to a common reset terminal. Control digits D4and D5 of the EOR 22 are appied to a set of six input gates 56 of thestaticizing control circuits 16.

STATICIZING CONTROL CIRCUITS 16 The staticizing control circuits 16include an address decoder 58 and a recognition circuit 28 which controla set of five gates 61-65 used to generate trigger input signals to thevarious counters. The five gates 61-65 are designated by the name of thecounter with which they are associated, viz TXC, TYC, TZC, TEC and TIC,respectively. The decoder 58 senses the address digit D5 of an EO andgenerates an enabling level corresponding to the counter specified bythis digit. The ve levels generated by decoder 58 are identified by thecounters with which they are associated. As described later, theselevels are used in gating addresses to the address `bus 10. The AEC andAIC levels are also generated by operation retrieval levels to bediscussed later. These operation retrieval levels are coupled by way ofor circuits to the TEC and TIC gates.

A set of gates 68, and 74 are used for generating control levels ROP,RIP and REP, respectively. These control levels are used during readingto and from the memory unit 1, in enabling the gates of the staticizingcounters XC, YC and ZC, and in the processing circuits 5. The ROI) gate68 is enabled by an E02 level. The RIP and REP gates 70 and 74 lareenabled by various ones of the elementary operation levels, andoperation retrieval levels which are applied through or circuits 72 and76, respectively.

The three address staticizing levels RXA, RYA and RZA are coupled to theR3, R4 and RS code generators (or encoders) 77, 78 and 79, respectively.Each of these generators applies to control bus 14, a three bit binarycode which identifies the corresponding X, Y and Z counter. (A three bitcode is sufficient to identify each of the severi counters and registerscoupled to the control bus 14.) The EC 2t) is identified by a three bitcode generated by code generator 80. The generator 80 is enabled by theRFEOU.) elementral control level or the output of an and gate 82. Thisgate is enabled by the E03 level and by a data dependent signal XeY. Thedata dependent signal for gate 82, in this instance, is received from aninverter circuit 83 connected to the output of comparator unit 84 in theprocessing circuits 5. The comparator output is normally low except whenasomar/9 9 the contents of the XC and YC counters are identical when itchanges to a high value. The inverter 83 changes the normal low signalto a high signal normally enabling the and gate 82.

The outputs of the control gates 68, 70, 74 and code generators R2, R3,R4 and R5 of the staticizing circuits 16 are applied to the control bus14. The various codes each designate one of counters and are decoded bycorresponding one of the decoder units R1, R2, R3, R4 and RS which arecoupled to the control bus 14.

The R1 code designates IC 6, the R2 code designates the EC 20, and theR3, R4 and R5 codes designate the counters XC, YC and ZC, respectively.The R6 and R7 codes designate the operand register and accumulator ofthe adder unit.

Gate 86 serves to gate the control digits D2 and D3 from the EORregister 22 to the control `bus 14. The gate 86 is enabled by an EXEO(1)level from the EO control circuits 24 and is inhibited by the outputfrom inverter 87. The inverter 87 output is high except when E03 and E04levels are present.

It is understood that, if desired, the various code generators R3, R4and RS can be replaced by a single encoding unit, and the variousdecoders R1-R7 can be replaced by a single decoder unit.

E CONTROL CIRCUITS 24 (FIGURE 3C) These circuits are used for generatingcontrol levels used in selecting and executing different ones of theelementary operations. The E0 operation digit D6 (bits 15-17) from theEOR 22 is applied to a set of three and gates 9i) whose outputs aredecoded by E0 operations decodcr 92 into a corresponding one of the liveEO levels E00, E01, E02, E03 and E04. The execution of the EOs isinitiated by EXEO flip-flop 94 which generates the EXEO(1) level at its1" output. The llipllop is controlled by a prime Hip-flop PEX 96. Thetlipllop 96 is set by various ones of the operation retrieval levels andin certain instances by the EO levels themselves by way of and gates 98and 99. The output of "and gate 98 sets the PEX Hip-flop 96 when anelementary operation is to be executed.

THE STATICIZING COUNTERS (FIGURE 3B) As described above, the inventionis exemplified in connection with a three-address type system and,accordingly, three staticizing counters XC, YC and ZC are used. Each ofthese counters has eighteen lip-ilops and can be incremented by one unitby a trigger pulse. A rst set of output gates 100, 101 and 102,respectively, couple the contents of XC, YC and ZC to the address bus 2,and a second set of output gates 103, 10S and 107, respectively, couplethe contents of these counters to the data bus 10. Common reset gates108, 109 and 110 are used to reset the counters under the control of theREP level and the outputs of decoder units R3, R4 and R5, respectively.The three counters are coupled to the data bus 1l) via three sets ofinput gates 111, 112 and 113, respectively, under the control of the RIPlevel and the outputs of decoder units R3, R4 and R5.

If desired, the binary counters can be replaced `by registers by using aseparate incrementer unit (not shown) coupled between address bus 2 anddata bus 10. Each time a counter is connected to the address bus it isalso connected to the incrementer unit. The count is then incremented ornot as required and returned to the transferring counter.

PROCESSING CIRCUITS (FIGURE 3D) The adder 116 may be an eighteen bit,parallel binary adder which receives one operand at one input from aneighteen stage operand register (OPR) 118. For convenience, variousshifting and overflow circuits which may be used with the adder unit arenot shown.

Information is gated to OPR 118 from data bus 10 10 by way of a set ofand gates 120 enabled by the RIP level and the output of the R6 decoder.A common reset is applied to OPR 118 by way of and gate 122 controlledby RIP level and the R6 decoder.

The second operand is applied to the second input of adder 116 from aneighteen stage accumulator unit (ACC) 124. A set of eighteen and gates126 connects the accumulator to the adder under the control of the REPlevel and the decoder R6. The accumulator register is also connected tothe data `bus 10 by way of a set of eighteen and gates 128 under thecontrol of the ROP level and the R7 decoder.

A common reset input of the accumulator is coupled to the output of afirst reset and gate 130 controlled by the REP level and the R7 decoder,and a second reset and gate 132 controlled by the R6 decoder. Theaccumulator 124 receives information from either the data bus 10 by wayof a set of and gates 136 or from the adder unit 116 by way of a set ofand gates 138. The first accumulator input gates are controlled by theRIP level and R7 decoder. The second accumulator input gates 138 arecontrolled by an add flip-llop (AD) 140. The flip-flop 14() is set bythe output from and gate 142 which is controlled by the R6 decoder.

The comparator unit 84 receives the output of the XC counter at a rstinput and the output of the YC counter at a second input. The singleoutput is a high level when the two inputs are identical.

OPERATION RETRIEVAL CIRCUITS (FIGURE 4) The generating circuits for theoperation levels used in obtaining instruction and elementary operationwords from the memory unit are shown in FIGURE 4. The retrieve nextinstruction level (RNIN(1)) is generated by a pair oi ilip-tlops 150,152. An RNIN flip-Hop 150 has its set and reset inputs coupled to the land f outputs of a start flip-flop (ST) 152. This tlip-llop is set byvarious ones of the elementary operation levels and by a start signalgenerated externally as by pushbutton 154. When closed the pusltbuttonactivates a pulse generator 156 which applies an input pulse to the setinput of the start liip-llop. A first set and gate 158 is used to gatethe start pulse to the flip-tlop. Second and third set and gates 160 and162 combine two different groups of elementary operation control levelsand apply a set signal to the ST flip-dop hen these control levels arepresent. The ST Hip-ilop is reset by a reset "and gate 164. The RNINU)level is used to generate the staticizing levels RXA, RYA and RZA forthe X, Y and Z counters, and the rst elementary operation level RFEO(1).The three addresses used with an instruction are read in sequence fromthe memory to the XC, YC and ZC under the control of the RXA, RYA andRZA ip-llops which are connected in cascade arrangement. The RXA levelis generated by a pair of Hip-flops comprising a RXA hip-Hop 176 and aprime llip-tlop X. The l and 0 outputs of the X flip-flop are coupled tothe set and reset inputs of the RXA flip-flop 170. The X flip-Hop is setby the output of and gate 174 under the control of the RNIN(1) level andthe output of code recognition circuit 49 (FIGURE 3C).

The RYA(1) and RZA(1) levels are generated by pairs of flip-Hops Y,RYAand Z,RZA. The Y prime Hip-flop is set by the output of and gate 176under the control of the RXA(1) level. The Z prime flip-flop is set bythe output of and gate 178 under the control of the RYA(1) level.

A pair of flip-flops the RFEO(1) level. of and level.

An RI level is provided by the output of or circuit 182 which receivesas inputs the RNIN(1), RXA(1), RYA(1) and RZA(1) levels.

A pair of Hip-flops NEO, RNEO are used to generate F and RFEC are usedto generate The F flip-flop is set by the output gate 180 under thecontrol of the RZA(1)

1. IN A DATA PROCESSING SYSTEM ARRANGED FOR EXECUTING AN INSTRUCTION BYA SEQUENCE OF ONE OR MORE MACHINE STEPS BEGINNING WITH AN INITIAL STEP,SAID INSTRUCTION BEING DEFINED BY AN INSTRUCTION WORD COMPRISING APLURALITY OF DIGITS INCLUDING OPERATION DIGITS, EACH OF SAID MACHINESTEPS BEING DEFINED BY A MACHINE WORD COMPRISING A PLURALITY OF DIGITSINCLUDING OPERATION DIGITS, A FIRST COUNTING MEANS FOR STORINGINSTRUCTION WORD ADDRESSES, A SECOND COUNTING MEANS FOR STORING MACHINEWORD ADDRESSES, STORAGE MEANS FOR STORING INSTRUCTION WORDS AND MACHINEWORD, MEANS RESPONSIVE TO AN ADDRESS SPECIFIED BY SAID FIRST COUNTINGMEANS FOR SELECTING A WORD FROM SAID STORAGE MEANS, MEANS FOR SENSINGSAID OPERATION DIGITS OF SAID SELECTED WORD, AND MEANS RESPONSIVE TOSAID MEANS FOR SENSING FOR INSERTING AN ADDRESS IN SAID SECOND COUNTINGMEANS AND FOR CHANGING SAID FIRST COUNTING MEANS TO SPECIFY ANOTHERADDRESS WHEN SAID SELECTED WORD IS AN INSTRUCTION WORD.